Meru walks through CXL, the technology suddenly on everyone's lips, using a road-and-warehouse picture. A CPU has a fixed number of DRAM slots because only so many dedicated lanes run across the motherboard. CXL sidesteps that limit by hanging extra 'memory warehouses' off the general-purpose PCIe road that is already there, so you can add as much memory as you want. The trade-off is speed: reading local DRAM takes 80-100 nanoseconds, while a trip out to CXL memory takes 170-250. That sounds bad until you remember not all data is equal. Hot data you touch constantly stays in fast local DRAM; data you rarely open lives in the cheap CXL warehouse, and the system barely slows down. Samsung packages this as CMM-D and SK Hynix as CMM-DDR5, the same idea under two names. Each CXL version adds tricks: 1.1 (2019) just expanded capacity, 2.0 added 'pooling' so several servers share one memory pool through a switch, like delivery firms sharing a warehouse instead of each over-building for peak season, and 3.x removes the partitions for fully shared memory. The version now arriving, CXL 3.2, moves the job of sorting hot from cold data out of software and bakes it into the hardware itself. For the memory makers, CXL is a new way to sell more DRAM.
Why it matters · CXL turns memory from a fixed slot count into an expandable warehouse, opening a fresh lane of DRAM demand for Samsung and SK Hynix.
Worth asking · Is CXL a genuine new growth lane for the memory makers, or a niche that AI's appetite for fast local HBM will overshadow?