Nvidia's plan for packaging its next generation of AI chips is running into real technical trouble, according to expert commentary shared from a JPMorgan hosted semiconductor seminar. Chipmakers can only pattern a fixed maximum area in a single lithography exposure, called a reticle, so bigger AI chip packages are built by stitching several reticle sized fields together, described as an N times reticle size package. Nvidia's upcoming Rubin Ultra chip uses a package roughly 5.5 times that reticle size, and testing on it is already running into implementation problems, with evaluations described as not going well. The bigger worry is what comes after: pushing the packaging technique to 9.5 times reticle size, which a future Nvidia chip would likely need, is expected to be extremely difficult, and a soldering related defect has already shown up in early testing for that larger format. If TSMC's advanced packaging platform, CoWoS-L, cannot be scaled up to handle a 9.5 times reticle package, it could put real limits on Nvidia's ability to build its next-next-generation architecture, code-named Feynman and expected around 2029. Intel is positioning an alternative structure called EMIB-T, which routes power and signals through vias built into a silicon bridge rather than one giant interposer, and claims it can support packages up to 12 times reticle size, more headroom than TSMC's current approach offers, potentially making Intel a fallback packaging supplier if TSMC hits a wall.
Why it matters · Nvidia's entire multi-year roadmap for bigger, faster AI chips depends on packaging technology that stitches multiple silicon dies into one giant chip, so if TSMC's packaging can't scale far enough, it becomes a hard ceiling on Nvidia's future chips, not a software problem you can patch, and it hands Intel's competing packaging tech a real opening to become the alternative supplier.
Worth asking · If TSMC's advanced packaging can't scale past roughly 5.5 times reticle size, that's a hard physical ceiling on how big Nvidia's future AI chips can get. Does this favor Intel's rival packaging approach becoming a serious alternative, or will TSMC solve the soldering problem before it actually delays anything?